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10 Limitations

Please be aware, that this chapter is version dependent so compare document version and software version to ensure both fit together.

10.1 Overall Limitations

This chapters describes an overview of system wide limitations for simulavr. Specific limitations see below.

10.2 CPU Limitations

This chapters describes an overview of limitations for simulavr. Specific limitations see below. This chapter focuses only on the Mega128 CPU.

The following hardware is not simulated by simulavr:

There are 64kByte of external memory automatically attached to the Mega128.

While Atmel changed some function details of the EEPROM, Watchdog Timer, Timer Subsystem, ADC, and USART / USI these subsystems have identical names but different functions. Therefore adding a new CPU to simulavr might end in reprogramming a subsystem!